Integrated circuits are manufactured by a highly complex and costly manufacturing process. During the first stages of this process a wafer is formed. A wafer includes multiple dice that are arranged in an ordered array of dice wherein the dice are parallel to each other, as illustrated in FIG. 1. Rectangular-shaped dice are arranged in columns and rows and are separated by scribe lines. The dice are characterized by a die X axis pitch 26 and a die Y axis pitch Y 28. Referring to FIG. 1, wafer 11 includes multiple dice 12(0,0)-12(k,j) that are collectively denoted 12. FIG. 1 also illustrates a global coordinate system 20 that includes X-axis 22 and Y-axis 24. The dice are arranged in parallel to these imaginary axes and are aligned with global coordinate system 20.
During the final manufacturing stages of the wafer the wafer is diced (or sawn) in order to separate between the different dice. The wafer is usually placed on a tape and after the dicing process the dice are then pulled away from each other, conveniently by using an ideally radial force. FIG. 2 illustrates a diced wafer 13, tape 37 and the forces (illustrated by arrows 35) that expand the diced wafer.
The sawing as well as the dice separation process result in a non-linear spatial relationships between the dice of the diced wafer. Each die can be shifted, rotated, sheered and stretched in relation to its previous (pre-dice) position and in relation to adjacent dice.
FIG. 3 illustrates an exemplary diced wafer 13. The dice (collectively denoted 14) of diced wafer 13 are not parallel to each other and diced wafer 13 is also misaligned (rotated) in relation to global coordinate system 20. The latter rotation can result from angular misalignments as well as mechanical inaccuracies.
Wafers and diced wafers are inspected for defects. The inspection can involve comparing between a die and a reference die. The following patents, all being incorporated herein by reference, illustrate various wafer inspection devices and methods as well as registration and alignment methods: U.S. Pat. No. 5,610,102 of Gardopee et al., U.S. Pat. No. 6,021,380 of Fredriksen et al., U.S. Pat. No. 6,937,753 of O'Dell et al., and U.S. Pat. No. 6,324,298 of O'Dell et al., and U.S. Pat. No. 4,981,529 of Tsujita.
Various prior art diced wafer inspection methods included locating a unique feature, comparing its location to an expected location, changing the scanning pattern in response to the differences between the actual location to the expected location and continuing to the next expected location of the unique feature.
There is a need to provide an inspection system that can inspect diced wafers and a method for inspecting diced wafers.